VLSI Architectures for Modern Error Correcting Codes by Xinmiao Zhang free pdf download

VLSI Architectures for Modern Error Correcting Codes by Xinmiao Zhang pdf.

VLSI Architectures for Modern Error Correcting Codes by Xinmiao Zhang

VLSI Architectures for Modern Error Correcting Codes by Xinmiao Zhang | Engineering Books.

Preface of VLSI Architectures for Modern Error Correcting Codes by Xinmiao Zhang pdf:
Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. It is difficult to follow the vast amount of literature to develop efficient very large scale integrated (VLSI) implementations of en/decoders for stateof-the-art error-correcting codes. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can also be used as a reference for graduate courses on VLSI design and error-correcting coding. Particularly, the emphases are given to soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications, due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures. 

Although many books have been published on both coding theory and circuit design, no book explains the VLSI architecture design of state-of-the-art error-correcting codes in great detail. High-performance error-correcting codes usually involve complex mathematical computations. Mapping them directly to hardware often leads to very high complexity. This book serves as a bridge connecting advancements in coding theory to practical hardware implementations. 

Instead of circuit-level design techniques, focus is given to integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The first part of this book (Chapters 1 and 2) introduces some fundamentals needed for the design and implementation of error-correcting codes. Specifically, Chapter 1 focuses on the implementation of finite field arithmetic, which is the building block of many error-correcting coding and cryptographic schemes. Chapter 2 briefly introduces commonly-used techniques for achieving speed, area, and/or power consumption tradeoffs in hardware designs. The second part (Chapters 3-7) of this book is devoted to the implementation of RS and BCH codes. Simplification techniques and VLSI architectures are presented in Chapter 3 for root computation of polynomials over finite fields, which is a major functional block in both hard- and soft-decision RS and BCH decoders. Chapter 4 gives the encoding and hard-decision decoding algorithms of RS codes and their implementation architectures. Transformations for lowering the complexity of algebraic soft-decision (ASD) RS decoding algorithms and their implementations are discussed thoroughly in Chapter 5. Chapter 6 focuses on the interpolation-based Chase decoder, which is one special case of ASD decoders, and it achieves a good performance-complexity tradeoff. BCH encoder and decoders, including both hard-decision and soft-decision Chase decoders, are presented in Chapter 7. The third part of the book (Chapters 8 and 9) addresses the implementation of LDPC decoders. Decoding algorithms and VLSI architectures for binary and non-binary LDPC codes are presented, compared, and discussed in Chapters 8 and 9, respectively. Chapter 1 of this book reviews finite field arithmetic and its implementation architectures. Besides error-correcting codes, such as RS, BCH, and LDPC codes, cryptographic schemes, including the Advanced Encryption Standard (AES) and elliptic curve cryptography, are also defined over finite fields. Definitions and properties of finite fields are first introduced. Then the implementation architectures of finite field operations using different representations of field elements, such as standard basis, normal basis, dual basis, composite field, and power presentation, are detailed and compared. The conversions among different representations are also explained. To assist the understanding of the en/decoder designs presented in later chapters, some fundamental concepts used in VLSI architecture design are introduced in Chapter 2. Brief discussions are given to pipelining, retiming, parallel processing, and folding, which are techniques that can be used to manipulate circuits to trade off speed, silicon area, and power consumption. More detailed discussions on these techniques are available in [21]. Chapter 3 discusses the implementation of root computation for polynomials over finite fields, which is a major block in hard-decision decoders and the factorization step of ASD decoders of RS and BCH codes. This is separated from the other Chapters on RS and BCH decoders to make the discussion more focused. Although exhaustive Chien search is necessary to find the roots of a general polynomial over finite field, the roots of an affine polynomial can be computed directly. Additionally, when the polynomial degree is at most three, the root computation is greatly simplified by converting the polynomial to a special format and making use of normal basis representation of finite field elements. RS codes are among the most extensively used error-correcting codes because of their good error-correcting capability and flexibility on the codeword length and code rate. Besides traditional systems, including optical and magnetic recording, wireless communications, and deep-space probing, RS codes are finding their ways in emerging applications, such as sensor networks and biomedical implants. Traditionally, hard-decision RS decoders are adopted in many systems, since they can achieve very high throughput with relatively low complexity. Chapter 4 first reviews the construction of RS codes, the encoding algorithms, and encoder architectures. Then the focus is given to popular harddecision decoding algorithms, such as the Peterson’s and Berlekamp-Massey algorithms, their complexity-reducing modifications, and corresponding VLSI implementation architectures. Chapters 5 and 6 present VLSI architectures for ASD decoders of RS codes. Compared to hard-decision decoders, soft-decision decoders correct more errors by making use of the channel reliability information. Over the past decade, significant advancement has been made on soft-decision RS decoding. In particular, by incorporating the reliability information from the channel into an interpolation process, ASD decoders achieve a better performance-complexity tradeoff than other soft-decision decoders. Nevertheless, the computations involved in ASD decoders are fundamentally different from those in harddecision decoders, and they would lead to very high hardware complexity if implemented directly. Many algorithmic and architectural optimization techniques have been developed to reduce the complexity of ASD decoders to practical level. These techniques are reviewed in Chapters 5 and 6. Chapter 5 discusses general ASD decoders, and Chapter 6 focuses on the Chase decoder, which can be interpreted as an ASD algorithm with test vectors consisting of flipped bits. 

The major steps of ASD decoders are the interpolation and factorization. Chapter 5 covers the re-encoding and coordinate transformation techniques that allow substantial complexity reduction on these two steps, the implementations of two interpolation algorithms, namely the K¨otter’s and Lee-O’Sullivan algorithms, as well as prediction-based and partial-parallel factorization architectures. When the multiplicities of all interpolation points are one in the Chase algorithm, additional modifications are enabled to simplify the interpolation-based decoding process as presented in Chapter 6. Examples are systematic re-encoding, backward-forward interpolation, eliminated factorization, and low-power Chien-search-based codeword recovery. Moreover, the interpolation-based approach also leads to substantial complexity reduction if applied to the generalized minimum distance (GMD) decoding. Chapter 6 also introduces a generalized backward interpolation that can eliminate arbitrary points of any multiplicity. Chapter 7 is dedicated to binary BCH codes. Similar to RS codes, BCH codes enjoy the flexibility on the codeword length and code rate. Nevertheless, compared to RS codes, BCH codes are more suitable for systems that have random bit errors and require low-complexity encoders and decoders. Example applications of BCH codes include optical communications, digital video broadcasting, and Flash memories. By making use of the binary property, the encoders and hard-decision decoders of RS codes discussed in Chapter 4 are simplified for BCH codes. Moreover, special treatment is given to 3-errorcorrecting BCH decoders, which are able to achieve very high throughput and are being considered for 100G optical transport network. A binary BCH code can be interpreted as a subcode of a RS code. Accordingly, the Chase ASD decoder architectures presented in Chapter 6 can be used to implement interpolation-based Chase BCH decoding. Nevertheless, the binary property allows additional transformations to be made to reduce the hardware complexity of these decoders. Chapter 8 discusses the implementation of binary LDPC codes. Although LDPC codes have higher implementation costs than RS and BCH codes and need long codeword length to achieve good error-correcting capability, they are gaining popularity due to their capacity-approaching performance. Binary LDPC codes are adopted in many applications and standards, such as 10GBase-T Ethernet, WiMAX wireless communications, digital video broadcasting, and magnetic and solid-state drives. The emphasis of this chapter is given to the VLSI architectures of the Min-sum decoders for quasi-cyclic (QC)-LDPC codes, which are usually employed in practical systems. The most popular decoding scheduling schemes, including the flooding, sliced messagepassing, layered and shuffled schemes, are reviewed and compared. Then the details of the computation units are presented. Moreover, techniques for reducing the power consumption of LDPC decoders are briefly discussed at the end of this chapter. They are applicable to any LDPC decoding algorithm. Compared to binary LDPC codes, non-binary LDPC codes can achieve better performance when the code length is moderate, and are more suitable for systems that have bursts of errors. 

As a result, they are being considered for emerging applications. Chapter 9 deals with the VLSI architectures for non-binary LDPC decoders. The major hardware bottlenecks of these decoders are complex check node processing and large memory requirement. The focus of this chapter has been given to the Min-max algorithm, which allows efficient tradeoff between the error-correcting performance and hardware complexity. Reviews are provided for various implementation approaches of the Min-max check node processing, such as the forward-backward, trellis-based path construction, syndrome-based, and basis-construction methods. Their relative complexity, advantages, drawbacks, and impacts on the memory requirement of the overall decoder are also discussed. Besides Min-max decoders, architectures are also presented in this chapter for another two types of popular decoders: the extended Min-sum and iterative majority-logic decoders. The preparation of this book was part of the task to be accomplished from the author’s National Science Foundation (NSF) Faculty Early Career Development (CAREER) Award. It was originally intended to be used as a reference book for graduate classes on error-correcting en/decoder hardware implementation. Nevertheless, it would also serve as an introduction for hardware engineers, system designers, and researchers interested in developing error-correcting en/decoders for various systems. The materials on finite field arithmetic and hardware design fundamentals in Chapters 1 and 2, respectively, are needed to understand the following chapters. Chapters 3 to 7.

for BCH and RS codes and Chapters 8, 9 for LDPC codes can be read independently. However, the chapters in these two groups need to be followed in the order they are presented. Although the architectures, transformation techniques, and simplification methods are presented for BCH, RS and LDPC codes in this book, they may be extended for other algorithms and systems. For example, an interpolation-based approach is also used in the fuzzy vault biometric encryption scheme, and message-passing algorithms can be employed to reconstruct compressively sensed signals. Most of the architectures presented in this book are from the author’s research results and papers. The author is grateful to her colleagues, friends, and students. Without them, this book would not have been possible. The author would like to thank Prof. Keshab Parhi for his encouragement and support of exploiting various research topics of interest. She is also grateful to Profs.

ShuLin and Daniel Costello for all their guidance, advise and kind support over the years. The author is thankful to Prof. Alexander Vardy for his encouragement for undertaking the research on ASD decoder design. Thanks are also due to Profs. and Drs. David Declercq, Fuyun Ling, Krishna Narayanan, Michael O’Sullivan, William Ryan, Gerald Sobelman, Myung Hoon Sunwoo, Bane Vasic, Zhongfeng Wang, and Yingquan Wu. It has been a real pleasure working and being friends with them.

The author’s research included in this book has been supported by the National Science Foundation, and the Air Force Office of Scientific Research. 

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