Digital System Design with VHDL Second edition by Mark Zwoli´nski.
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2 Combinational logic design
3 Combinational logic using VHDL gate models
4 Combinational building blocks
5 Synchronous sequential design
6 VHDL models of sequential logic blocks
7 Complex sequential systems
8 VHDL simulation
9 VHDL synthesis
10 Testing digital systems
11 Design for testability
12 Asynchronous sequential design
13 Interfacing with the analogue world
Appendix A VHDL standards
Appendix B Verilog
Appendix C Shared variable packages
Answers to selected exercises
About this book:
When the first edition of this book was published, the idea of combining a text on digital design with one on VHDL seemed novel. At about the same time, several other books with similar themes were published. This book has now been adopted by several universities as a core text. Moreover, the first edition has now been translated into Polish and a low-cost edition has been produced for the People’s Republic of China. This success and the competition convinced me that the idea had been good, but I was not convinced that I had achieved perfection the first time. This new edition corrects what I now feel to have been a mistake in the first version and adds two important topics. These changes are described later in this preface.
This book is intended as a student textbook for both undergraduate and postgraduate students. The majority of VHDL books are aimed at practising engineers. Therefore, some features of VHDL are not described at all in this book.
Equally, aspects of digital design are covered that would not be included in a typical VHDL book. Syllabuses for electrical, electronic and computer engineering degrees vary between countries and between universities or colleges. The material in this book has been developed over a number of years for second- and third-year undergraduates and for postgraduate students. It is assumed that students will be familiar with the principles of Boolean algebra and with combinational logic design. At the University of Southampton, the first-year undergraduate syllabus also includes introductions to synchronous sequential design and to programmable logic. This book therefore builds upon these foundations. It has often been assumed that topics such as VHDL are too specialized for second-year teaching and are best left to final-year or postgraduate courses. There are several good reasons why VHDL should be introduced earlier into the curriculum. With increasing integrated circuit complexity, there is a need from industry for graduates with knowledge of VHDL and the associated design tools. If left to the final year, there is little or no time for the student to apply such knowledge in project
work. Second, conversations with colleagues from many countries suggest that today’s students are opting for computer science or computer engineering courses in preference to electrical or electronic engineering. VHDL offers a means to interest computingoriented students in hardware design. Finally, simulation and synthesis tools are now mature and available relatively cheaply to educational establishments on PC platforms.
Changes in the second edition
ith hindsight, my mistake was to use std_ulogic instead of std_logic in most of the examples. From a purely educational point of view, the decision was correct as such usage would clearly indicate in simulation when outputs of blocks had been inadvertently joined together. From a practical point of view, this usage is at odds with most industrial practice and can cause problems with some EDA (electronic design automation) tools. All the examples have been revised to use std_logic. Several of the examples have also been simplified (e.g. by using direct instantiation). At the time of the first edition, there were some EDA tools that only supported the 1987 standard of VHDL. These have largely disappeared and therefore I have tended to use constructs from the newer 1993 standard in preference in this edition. There has also been a 2002 revision to the standard. Although there are almost no tools that support the new standard at the time of writing, the changes are minimal and the only significant change (the form of shared variables) has been extensively discussed in Appendix C. I was also swimming against the tide in insisting on the use of the IEEE numeric_std package (as opposed to std_logic_arith), but I think I have been proved correct in that choice.
The two major additions take two forms. First, several chapters now include sections on writing testbenches. The verification of VHDL models by simulation is critical to producing correct hardware. It is reasonable to estimate that at least half of all VHDL written is in the form of testbenches for verifying models. Because this aspect is so important, the material has been included in the chapters where it is needed, not in a single chapter on testbench design. I would strongly encourage the reader to simulate the models in the text and to use the testbench examples to assist in this.
The second addition is a new chapter on VHDL-AMS and mixed-signal modelling. All digital hardware has to interact with the ‘real’ world at some point. Although mixed-signal simulators have been available for over 15 years, their use has been limited by the difficulty in writing interface models between the digital and analogue domains. VHDL-AMS integrates the two worlds and several mixed-signal simulators are now available. This chapter is not intended to be a comprehensive tutorial on converter design, nor on all the details of VHDL-AMS, but I hope it will encourage designers to attempt to model their systems as a whole.
Structure of this book
Chapter 1 introduces the ideas behind this book, namely the use of electronic design automation tools and CMOS and programmable logic technology. We also consider some engineering problems, such as noise margins and fan-out. In Chapter 2, the principles of Boolean algebra and of combinational logic design are reviewed. The important matter of timing and the associated problem of hazards are discussed. Some basic techniques for representing data are discussed.
VHDL is introduced in Chapter 3 through basic logic gate models. The importance of documented code is emphasized. We show how to construct netlists of basic gates and how to model delays through gates. We also discuss parameterized models and constant and unconnected inputs and outputs. The idea of using VHDL to verify VHDL models by using testbenches is introduced. Finally, we briefly introduce the concept of configurations.
In Chapter 4, a variety of modelling techniques are described. Combinational building blocks, buffers, decoders, encoders, multiplexers, adders and parity checkers are modelled using a range of concurrent and sequential VHDL coding constructs. The VHDL models of hardware introduced in this chapter and in Chapters 5, 6 and 7 are, in principle, synthesizable, although discussion of exactly what is supported is deferred until Chapter 9. Testbench design styles are again discussed here. In addition, the IEEE dependency notation is introduced.
Chapter 5 is probably the most important chapter of the book and discusses what might be considered the cornerstone of digital design: the design of finite state machines. The ASM chart notation is used. The design process from ASM chart to D flip-flops and next state and output logic is described. VHDL models of state machines are introduced. Chapter 6 introduces various sequential building blocks: latches, flip-flops, registers, counters, memory and a sequential multiplier. The same style as in Chapter 4 is used, with IEEE dependency notation, testbench design and the introduction of VHDL coding constructs. In Chapter 7 the concepts of the previous three chapters are combined. The ASM chart notation is extended to include coupled state machines and registered outputs, and hence to datapath-controller partitioning. From this, we explain the idea of instructions in hardware terms and go on to model a very basic microprocessor in VHDL. This provides a vehicle to introduce VHDL subroutines and packages.
VHDL remains primarily a modelling language. Chapter 8 describes the operation of a VHDL simulator. The idea of event-driven simulation is first explained and the specific features of a VHDL simulator are then discussed. Although the entire VHDL language can be simulated, some constructs simulate more efficiently than others; therefore techniques for writing models that are more efficient are discussed. File operations are also discussed in this chapter because such functionality is only appropriate to simulation models.
The other, increasingly important, role of VHDL is as a language for describing synthesis models, as discussed in Chapter 9. The dominant type of synthesis tool available today is for RTL synthesis. Such tools can infer the existence of flip-flops and latches from a VHDL model. These constructs are described. Conversely, flip-flops can be created in error if the description is poorly written, and common pitfalls are described. The synthesis process can be controlled by constraints. Because these constraints are outside the language, they are discussed in general terms. Suitable constructs for FPGA synthesis are discussed. Finally, behavioural synthesis, which promises to become an important design technology, is briefly examined.
Chapters 10 and 11 are devoted to the topics of testing and design for test. This area has often been neglected, but is now recognized as being an important part of the design process. In Chapter 10 the idea of fault modelling is introduced. This is followed by test generation methods. The efficacy of a test can be determined by fault simulation. At the time of writing, there are no commercial VHDL-based fault simulators available. The final section of this chapter shows how fault modelling and fault simulation can be performed using a standard VHDL simulator. The VHDL code also introduces constructs such as pointers and shared (global) variables.
In Chapter 11, three important design-for-test principles are described: scan path, built-in self-test (BIST) and boundary scan. This has always been a very dry subject, but a VHDL simulator can be used, for example, to show how a BIST structure can generate different signatures for fault-free and faulty circuits. Boundary scan uses a subset of VHDL to describe the test structures used on a chip, and an example is given. We use VHDL as a tool for exploring anomalous behaviour in asynchronous sequential circuits in Chapter 12. Although the predominant design style is currently synchronous, it is likely that digital systems will increasingly consist of synchronous circuits communicating asynchronously with each other. We introduce the concept of the fundamental mode and show how to analyze and design asynchronous circuits. We use VHDL simulations to illustrate the problems of hazards, races and setup and hold time violations. We also discuss the problem of metastability.
The final chapter introduces VHDL-AMS and mixed-signal modelling. Brief descriptions of Digital to Analogue Converters (DACs) and Analogue to Digital Converters (ADCs) are given. VHDL-AMS constructs to model such converters are given. We also introduce the idea of a Phase-Locked Loop (PLL) here and give a simple mixed-signal model. Three appendices are included. The first appendix lists the various VHDL-related standards and speculates on the future development of VHDL. The second appendix briefly describes the Verilog hardware description language. Verilog is the major alternative to VHDL and it is likely that designers will have to be familiar with both. The third appendix covers shared variables, in particular the differences between the 1993 and 2002 versions.
At the end of each chapter a number of exercises have been included. These exercises are almost secondary to the implicit instruction in each chapter to simulate and, where appropriate, synthesize each VHDL example. To perform these simulation and synthesis tasks, the reader may have to write his or her own testbenches and constraints files. The examples are available on the World Wide Web at the address given in the next section.
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Digital System Design with VHDL 2nd edition by Mark Zwoli´nski pdf.
⏩Author: Mark Zwoli´nski
⏩Copyright © Pearson Education Limited 2000, 2004
⏩Size: 23.6 MB
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